Download Three Dimensional System Integration: IC Stacking Process by Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic PDF
By Antonis Papanikolaou, Dimitrios Soudris, Riko Radojcic
Three Dimensional method Integration: IC Stacking From method expertise to method layout Edited through: Antonis Papanikolaou Dimitrios Soudris Riko Radojcic third-dimensional (3D) built-in circuit (IC) stacking permits packing extra performance, in addition to integration of heterogeneous fabrics, units, and signs, within the similar house (volume). This ends up in patron electronics (e.g., cellular, hand held units) that can run extra strong functions, comparable to full-length videos and 3D video games, with longer battery lifestyles. This expertise is so promising that it really is anticipated to be a mainstream expertise lower than 10-15 years from its unique belief. to accomplish this kind of finish product, alterations within the whole production and layout means of digital platforms are occurring. This ebook offers an outline of the total trajectory from uncomplicated method know-how matters to the layout on the approach point of 3 dimensionally built-in nano-electronic platforms. actual layout and layout on the structure and approach point are emphasised during this ebook, because the expertise has matured to the purpose that those matters became vitally important. This booklet is meant for an viewers with a simple snatch of electric engineering suggestions together with a few familiarity with fabrication of semiconductor units, Very huge Scale Integration (VLSI) and desktop structure. •Covers the full variety of 3D chip stacking subject matters in this kind of means non-expert (in 3D integration) reader can comprehend precisely what this expertise is, why it's useful, the way it alterations traditional practices and the way it could possibly have an effect on his/her paintings; •Provides a high-level (tutorial-like) description of 3D method integration that would conceal concerns starting from method know-how and production of 3D platforms to the layout of 3D parts and full platforms; •First publication to supply not just a high-level view of the complete box of 3D integration, but in addition an knowing of the interactions among many of the stages of layout and manufacturing.
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Additional info for Three Dimensional System Integration: IC Stacking Process and Design
The next TSV-enabled wafer is inverted onto this 4 Homogeneous 3D Integration 55 Fig. 3 SEM micrograph of a two-wafer stack and one of its TSVs TSV Silicon Dielectric(SiO2/SiN) Gate poly STI (Shallow trench isolation) W (Tungsten TSV & vias) Al or Cu interconnect (M1– M5) Cu bondpoints (M6, top metal) Al padout Fig. 4 A finished three-wafer stack padded out with aluminum for normal wire bonding new surface, face-down, and bonded as before. Thinning, metallizing, and bonding are repeated as desired.
2 Stack Bonding Two issues are dominant in the development of a proper bonding technique. The first is establishing the bonding process itself together with the appropriate materials. The second involves maintaining the mechanical stability of the individual tiers and the complete stack during and after the bonding process is complete. Early attempts to build 3D ICs used adhesives as the bonding technology . Experiments indicated that the TSV pitch could not be scaled to less than 6 mm with an adhesive bond due to outgassing from the adhesive.
6 Illustration of capacitance for a cylindrical structure in Si substrate where L is the TSV length, which is equal to the substrate thickness T, ei is the dielectric constant of the insulator, d = 2a is the diameter of the Cu conductive plug, and D = 2b is the TSV diameter. Therefore, the thickness of the insulator oxide is: t = (b − a) = (D − d )/2. 3) becomes CINS = 2p e iT . 4) 3 TSV Characterization and Modeling 39 Fig. 7 Accumulation, depletion and maximum depletion regions on a C–V curve for a TSV characterized as a metal–insulator–semiconductor capacitor Depletion region: In a p-type substrate, if a positive enough voltage VTSV is applied to the TSV with respect to the substrate, a depletion region and consequently a depletion region capacitance will be formed.